With the development of the electrical technology, a FET with high integrity and operation speed is required. However, the operation speed of the FET is difficult to be improved due the steady electron (hole) migration rate in a silicon substrate, thus the utility of the FET may be limited.
In comparison with silicon, silicon germanium (SiGe) has a greater lattice constant, thus when SiGe is utilized to form a drain/source structure of a FET, a extrusion stress can be imposed to the channel of the FET and the hole-mobility in the channel region can be enhanced. Currently, this SeGe drain/source structure has been provided by the prior art to improve the performance of a FET device.
FIG. 1 illustrates a cross sectional view of a FET 100 in accordance with the prior art. The FET 100 comprises a gate structure 102 and a SiGe drain/source structure 101 formed on a silicon substrate 105, wherein the SiGe drain/source structure 101 is formed by forming a SeGe material in a recess 106 formed in the silicon substrate 105 alongside the gate spacer 104. The SiGe material formed in the recess 106 is then subjected to a thermal annealing process to complete the process in fabricating the FET 100.
However, the etching reagent used to form the recess 106 may undercut the silicon substrate 105, such that the recess 106 may extend laterally into the channel region beneath the gate structure 102. After the SiGe material is annealed, the SiGe material may swell to form a diamond like SiGe drain/source structure 101 filling the recess 106, thus the channel distance may be shortened due to the extrusion of the SiGe drain/source structure 101, and a punch through effect triggered by the shortened channel may occur more easily.
Therefore, it is necessary to provide an improved method for fabricating a FET to obviate the drawbacks and problems encountered from the prior art.